In the first conventional method of providing a high-density substrate used as a semiconductor device in a BGA (Ball Grid Array: hereinafter simply referred to as the EGA) semiconductor device or an LGA (Land Grid Array: hereinafter simply referred to as the LGA) semiconductor device, a laminate substrate is used to provide an intermediate wiring layer between a first surface and a second surface of a substrate. In addition to providing wires onto the first surface and the second surface, wires are routed via the intermediate wiring layer to secure the wiring area and provide a high-density substrate.
In the second method, the diameter of a through-hole is reduced to secure the area and to provide the through-hole with multiple functions.
A conventional technique for providing a through-hole with multiple functions (see, for example, Japanese Patent Laid-Open No. 58-110094) will be described below.
The conventional technique includes a method of forming one through-hole and a plurality of independent lands and wires around the through-hole, subjecting a substrate to electroless plating, and then cutting a plated portion inside the through-hole. In this case, a small-sized through-hole requires an advanced processing technique for subsequently dividing the inside of the through-hole.
In recent years, in double-sided substrates, which are often used as wiring substrates for semiconductor devices, there has been an increasing demand for regulating arrangement of wires for plating and conducting wires in response to an increased number of pins, as well as wire routing in response to an increased number of through-holes and improvement in the accuracy of electrical characteristics.
In connection with the above description, a typical substrate design will be described below with reference to the drawings.
FIG. 12 is a plan view showing the first surface of a conventional substrate. FIG. 13 is a plan view showing the second surface of the conventional substrate. FIG. 14 is a side view showing the appearance of a semiconductor device using the conventional substrate.
In FIGS. 12, 13, and 14, reference numerals 1, 2, and 3 denote a substrate, a through-hole, and an internal terminal, respectively. Reference numerals 4, 5, and 6 denote a conducting wire, an external terminal electrode, and a wire for plating, respectively. Reference numerals 7, 9, 10, and 11 denote an outer peripheral wire for plating, a molding resin, a resist, and a solder ball, respectively.
The conventional substrate 1 is a double-sided substrate including, as electric wiring making up an internal circuit, a plurality of pairs of the internal terminal 3 and the conducting wire 4, which are connected together, arranged on the first surface as shown in FIG. 12 and a plurality of sets each made up of one external terminal electrode 5, one conducting wire 4, and one through-hole 2, which are connected together, arranged on the second surface opposite to the first surface as shown in FIG. 13. Moreover, to allow all the electric wires to be electrically connected together into one conducting wire so as to be subjected to an electroplating process at a time, the outer peripheral wire 7 for plating and multiple wires 6 for plating are arranged on the second surface as shown in FIG. 13; the wires 6 for plating are formed so as to be connected to the outer peripheral wire 7 for plating and each electrically connected to one set of the external terminal electrode 5 and the through-hole 2.
In the semiconductor device using the substrate 1, an increase in the number of pins increases the number of electric wires arranged so as to make up the internal circuit. This complicates the arrangement of the conducting wire 4 and the through-hole 2, limiting a design space. As a result, the degree of freedom for design of a double-sided substrate decreases significantly.
To avoid this problem, a laminate substrate may be used. However, since the laminate substrate increases costs, a method of improving for maximizing the design space for a double-sided substrate is required.
Furthermore, collective resin molding is generally used for the BGA semiconductor device and the LGA semiconductor device. In this case, after the collective molding, the resulting substrate is divided into individual semiconductor devices. Simultaneously with the division, the outer peripheral wire 7 for plating is cut off, and the wires 6 for plating electrically connected to the outer peripheral wire 7 for plating are also cut off for division and disconnected from the outer peripheral wire 7 for plating.
In the semiconductor devices resulting from the division, as shown in FIG. 14, the wires 6 for plating electrically connected to the internal circuit are exposed from a side surface of the semiconductor device. Thus, in the handling of the semiconductor device, static electricity may be applied to the internal circuit through the exposed portions of the wires 6 for plating, or when the semiconductor device is mounted, an adjacent electronic component or mounting solder may contact the exposed portions of the wires 6 for plating. This results in an electrical defect, preventing products from maintaining acceptable quality.